1. Technical Field
The current disclosure relates to an apparatus and a method of interconnect redundancy and timing analysis of an integrated circuit.
2. Background
Three dimensional integrated circuit is different from the conventional two dimensional integrated circuit which is a chip having two or more tiers of active electronic components being integrated both vertically and horizontally into a single circuit. Therefore, the three dimensional integrated circuit is able to conquer the difficulty of conforming different transistors having different functions onto a single integrated circuit. In current routing types of the three dimensional integrated circuit, Through-Silicon Via (TSV) is inserted into the chip and implementing routing to change the signal connecting position in the redistribution layer on the upper side and lower side of the chip, and stacking chips by bonding micro bumps. Therefore, signal communication between different chips in a three dimensional integrated circuit is able to be transmitted vertically and horizontally by the TSV, redistribution layer and micro bumps.